Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Programmers model
Bits Name Description
[8] CFI Controls whether a corrected error generates a fault handling interrupt.
SBZ on non-correctable errors else:
0 The GIC-600AE does not assert a fault handling interrupt for corrected errors
1 The GIC-600AE asserts a fault handling interrupt, the fault_int signal, when a corrected error occurs
[7:5] - Reserved, RAZ
[4] UE Uncorrected error.
RAZ/WI for all records except GICT error record (0) else:
0 Do not send External abort with transaction
1 Send External abort with transaction. See 4.15.7 Bus errors on page 87.
[3] FI Fault handling interrupt.
SBZ on Correctable Error (CE) records else:
0 Fault handling interrupt is not generated on any error
1 Fault handling interrupt, fault_int signal, is generated on all uncorrectable errors
[2] UI Error recovery interrupt for uncorrected error.
SBZ on CE records else:
0 Error recovery interrupt is not generated on any error
1 Error recovery interrupt, err_int signal, is generated on all uncorrectable errors
[1:0] - Reserved, RAZ
5.8.3 GICT_ERR<n>STATUS, Error Record Primary Status Register
This register indicates information relating to the recorded errors.
Configurations
This register is available in all configurations.
Attributes
Width 32-bit
Functional group See 5.8 GICT register summary on page 147 for the address offset, type,
and reset value of this register.
Usage constraints
If GICD_SAC.GICTNS == 0, then only Secure software can access the functions of this register.
Bit descriptions
Figure 5-38: GICT_ERR<n>STATUS bit assignments
SERR
31 30 29 28 27 26 25 24 23 22 21 20 19 16 15 8 7
0
IERRReservedUETCEOFERUEVAV
ReservedMV
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