Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Components and configuration
Table 3-10: Transaction acceptance
Transaction type Maximum number of transactions allowed
Read Unlimited
Write Unlimited
Combined Unlimited
Any leading wdata signal is registered and held until the awaddr signal arrives. These signals are
described in A.5 ACE-Lite interface signals on page 254.
•
The MSI-64 Encapsulator requires a data bus that has a width of 64 bits or
greater.
•
The ACE-Lite manager port never issues more than two addresses before the
wlast signal asserts.
3.4.2 MSI-64 Encapsulator configuration
The MSI-64 Encapsulator does not have any configurable parameters at design time. However, if
this block is generated in your RTL design, it has several options that you can configure at build
time.
The MSI-64 Encapsulator is generated as part of any GIC configuration that includes an MSI-64
enabled ITS.
The following table shows the options for the MSI-64 Encapsulator that you can configure at build
time.
Table 3-11: Configurable options for the MSI-64 Encapsulator
RTL parameter Function Range of options
DATA_WIDTH Specifies the width of rdata and wdata data signals 64, 128, 256
ADDR_WIDTH Specifies the width of araddr and awaddr address signals 17-48
AWUSER_WIDTH Specifies the width of awuser signal 1-128
ARUSER_WIDTH Specifies the width of aruser signal 1-128
RUSER_WIDTH Specifies the width of ruser signal 1-128
WUSER_WIDTH Specifies the width of wuser signal 1-128
BUSER_WIDTH Specifies the width of buser signal 1-128
DID_WIDTH Specifies the width of the DeviceID 3-20
WID_WIDTH Specifies the width of wid signal 1-32
RID_WIDTH Specifies the width of rid signal 1-32
FWD_REG_TYPE Register slice type on forward AW, AR, and W channels
0 None
1 Reverse
2 Forward
3 Full
Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved.
Non-Confidential
Page 41 of 268
To Next Page
Loading...
Need help?
General
