Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Operation
The ITS caches are automatically managed and invalidated as necessary when the GITS_BASERn
registers are updated. Therefore, software intervention is not required. However, to aid debug and
integration testing, you can force invalidation of the appropriate cache by setting the relevant bit in
the GITS_FCTLR register.
A forced invalidation of the Event cache abandons all locked entries.
The GITS_OPR and GITS_OPSR registers control cache locking, when software provides
the DEVICE_ID, EVENT_ID, and the correct GITS_OPR.LOCK_TYPE (ITS lock = 2). The GIC
attempts to perform the lock, and reports the status in GITS_OPSR. If the lock succeeds,
GITS_OPSR.REQUEST_COMPLETE == 1 and GITS_OPSR.REQUEST_PASS == 1.
Each cache set is 2-way set associative. Only one entry can be locked in each cache set. Any
attempt to lock both ways in a set, reports as failed in GITS_OPSR. You can also use the GITS_OPR
register to unlock entries that are locked.
The GITS_OPR register has two test features:
Trial Tests the mapping by writing a DeviceID and EventID to GITS_OPR
with GITS_OPR.LOCK_TYPE = 1 (Trial). This causes the ITS to translate
the supplied DeviceID and, or EventID pair, and report the generated
translation data in GITS_OPSR. The GIC also reports whether the
translation fails, GITS_OPSR.REQUEST_PASS == 0, or if it hit a locked entry,
GITS_OPSR.ENTRY_LOCKED. The interrupt is not set to pending.
Track Can be used to detect the arrival of a certain EventID and, or DeviceID pair,
which the GIC reports by setting GITS_OPSR.REQUEST_COMPLETE.
While any GITS_OPR operation, other than Track, is in progress, the
GITS_OPSR.REQUEST_IN_PROGRESS bit is set and no further updates are accepted by
GITS_OPR until the previous operation completes. To ensure that the operation is accepted, we
recommend that the GITS_OPR value is read after writing. You can abort Track operation by writing
GITS_OPR.LOCK_TYPE == Track abort.
4.9.2 ITS commands and errors
Each ITS detects a wide range of command errors and translation errors, and reports them in
Armv8.2 RAS-compliant error records in the Distributor.
The ITS record error syndromes comprise four groups that each have separate enables in the
GITS_FCTLR register. The following table shows the ITS record error syndrome groups.
Table 4-3: ITS record error syndrome groups
Group Control
ACE-Lite subordinate interface write translation errors. Only when the ITS has a separate ACE-Lite
subordinate port.
GITS_FCTLR.AEE (Access Error
Enable)
Translation errors on incoming writes to GITS_TRANSLATER GITS_FCTLR.UEE (Unmapped Error
Enable)
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