Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Operation
For all ECC schemes that are used in the GIC-600AE, the correction code is 0 when all data in the
RAM is 0.
4.14 Performance Monitoring Unit
The GIC-600AE contains a PMU for counting the main GIC events from the Distributor and any
configured ITS blocks on the same chip.
The PMU does not track Redistributor events. Software can count the delivery of
PPI and SGI interrupts by recording calls to the core interrupt service routine.
The GIC events are described in Table 5-60: GICP_EVTYPERn.EVENT field encoding on page
165.
The PMU has five counters with snapshot capability and overflow interrupt.
Secure and Non-secure interrupts are counted together, so Non-secure software cannot, by
default, access the GICP (PMU) register space. However, Secure software can decide to allow
access. Non-secure software can be given access to the GICP (PMU) register space by either:
•
Software programming the GICD_SAC.GICPNS bit to 1
•
Setting the gicp_allow_ns tie-off signal HIGH, during silicon integration
If GICD_CTLR.DS == 1, the GICP register space is accessible to all software.
Count configuration
Each PMU counter can be programmed individually to count a range of events.
To configure a counter:
1.
Program the counter GICP_EVCNTRn to a known value. This value could be 0 to count events,
or a higher number to trigger an overflow after a known number of events.
2.
Program the associated GICP_EVTYPERn to count the required event
3.
Program the required filter type for the event by programming GICP_FRn
4.
Enable the counter by programming the corresponding bit in GICP_CNTENSET0
5.
Repeat the previous steps for all counters that are required
6.
Enable the global count enable in GICP_CR.E
PMU registers, other than enables, do not have resets and must be programmed
before use.
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