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CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Signal descriptions
A.5 ACE-Lite interface signals
The following table shows the GIC-600AE ACE-Lite signals.
Table A-5: ACE-Lite subordinate interface signals
Subordinate write address channel signals
Signal Direction Description
There are multiple versions of this bus. Buses that have _its[_<num>] are dedicated ITS subordinate ports for GITS_TRANSLATER
only. There is always one port that has no _its suffix that is used for all registers except GITS_TRANSLATER. This port is used for all
registers in monolithic configurations.
awuser_[its[_<num>]]_s[n:0] Input Optional User signal. For GICD interface, n = axis_awuser_width−1. For an ITS switch, n
is a minimum of did_width−1.
Indicates the DeviceID of writes to GITS_TRANSLATER if MSI_64 is not configured.
awaddr_[its[_<num>]]_s[n:0] Input The write address gives the address of the first transfer in a write burst transaction. Where n
= axis_addr_width−1.
awid_[its[_<num>]]_s[n:0] Input This signal is the identification tag for the write address group of signals. Where n = axis_
wid_width−1.
awlen_[its[_<num>]]_s[7:0] Input The burst length gives the exact number of transfers in a burst. This information determines
the number of data transfers associated with the address.
awsize_[its[_<num>]]_s[2:0] Input This signal indicates the size of each transfer in the burst.
awburst_[its[_<num>]]_s[1:0] Input The burst type and the size information, determine how the address for each transfer within
the burst is calculated.
awprot_[its[_<num>]]_s[2:0] Input This signal indicates the privilege and security level of the transaction, and whether the
transaction is a data access or an instruction access.
awvalid_[its[_<num>]]_s Input This signal indicates that the channel is signaling valid write address and control information.
awready_[its[_<num>]]_s Output This signal indicates that the subordinate is ready to accept an address and associated control
signals.
awcache_[its[_<num>]]_s[3:0] Input This signal indicates how transactions are required to progress through a system.
awdomain_[its[_<num>]]_s[1:0] Input This signal indicates the Shareability domain of a write transaction.
awsnoop_[its[_<num>]]_s[3:0] Input This signal indicates the transaction type for Shareable write transactions.
awbar_[its[_<num>]]_s[1:0] Input This signal indicates a write barrier transaction.
Subordinate write data channel signals
Signal Direction Description
wstrb_[its[_<num>]]_s[n:0] Input This signal indicates which byte lanes hold valid data. There is one write strobe bit for every 8 bits
of the write data bus.
wdata_[its[_<num>]]_s[n:0] Input Write data, where n = axis_data_width−1
wvalid_[its[_<num>]]_s Input This signal indicates that valid write data and strobes are available.
wready_[its[_<num>]]_s Output This signal indicates that the subordinate can accept the write data.
wlast_[its[_<num>]]_s Input This signal indicates the last transfer in a write burst.
Subordinate write response channel signals
Signal Direction Description
bid_[its[_<num>]]_s[n:0] Output This signal is the ID tag of the write response. Where n = axis_wid_width−1.
bvalid_[its[_<num>]]_s Output This signal indicates that the channel is signaling a valid write response.
bready_[its[_<num>]]_s Input This signal indicates that the manager can accept a write response.
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