ARM CoreLink GIC-600AE

Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Programmers model
5.8 GICT register summary
The GIC-600AE trace and debug functions are controlled through registers that are identified with
the prefix GICT.
All registers comply with the Arm
®
Architecture Reference Manual Supplement Reliability,
Availability, and Serviceability (RAS), for Armv8-A, except for the GICT_PIDR* and GICT_CIDR*
registers.
The GICD_SAC.GICTNS bit controls whether Non-secure software can access the
GICT registers.
Table 5-45: GICT register summary
Offset Name Type Reset Width Description
0x0000 + (n × 64) GICT_ERR<n>FR RO Record dependent 64 Error Record Feature Register
0x0008 + (n × 64) GICT_ERR<n>CTLR RW 0x0 64 Error Record Control Register
0x0010 + (n × 64) GICT_ERR<n>STATUS RW Record dependent 64 Error Record Primary Status register
0x0018 + (n × 64) GICT_ERR<n>ADDR RW Unknown 64 Error Record Address Register
0x0020 + (n × 64) GICT_ERR<n>MISC0 RW Unknown 64 Error Record Miscellaneous Register 0
0x0028 + (n × 64) GICT_ERR<n>MISC1 RW Unknown 64 Error Record Miscellaneous Register 1
0xE000 GICT_ERRGSR RO 0x0 64 Error Group Status Register
0xE008- 0xE7FC - - - - Reserved, RAZ/WI
0xE800- 0xE808 GICT_ERRIRQCR<n> RW 0x0 64 Error Interrupt Configuration Registers
0xE810- 0xFFB8 - - - - Reserved, RAZ/WI
0xFFBC GICT_DEVARCH RO 0x47700A00 32 Device Architecture register
0xFFC0- 0xFFC4 - - - - Reserved, RAZ/WI
0xFFC8 GICT_DEVID RO Configuration dependent 32 Device Configuration register
0xFFCC - - - - Reserved, RAZ/WI
0xFFD0 GICT_PIDR4 RO 0x44 32 Peripheral ID 4 register
0xFFD4 GICT_PIDR5 RO 0x00 32 Peripheral ID 5 register
0xFFD8 GICT_PIDR6 RO 0x00 32 Peripheral ID 6 register
0xFFDC GICT_PIDR7 RO 0x00 32 Peripheral ID 7 register
0xFFE0 GICT_PIDR0 RO 0x95 32 Peripheral ID 0 register
0xFFE4 GICT_PIDR1 RO 0xB4 32 Peripheral ID 1 register
0xFFE8 GICT_PIDR2 RO 0x3B 32 Peripheral ID 2 register
0xFFEC GICT_PIDR3 RO 0x00 32 Peripheral ID 3 register
0xFFF0 GICT_CIDR0 RO 0x0D 32 Component ID 0 register
0xFFF4 GICT_CIDR1 RO 0xF0 32 Component ID 1 register
0xFFF8 GICT_CIDR2 RO 0x05 32 Component ID 2 register
0xFFFC GICT_CIDR3 RO 0xB1 32 Component ID 3 register
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