Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Functional Safety
6.5.2 Resets
Each stitched level has two resets, which are active-LOW.
The resets that are used for wrap components are:
reset_n This signal is the reset for primary mission-critical logic
reset_n_fdc This signal is the reset for redundant logic
The resets that are used for stitched domain modules, or the top level, are:
<domain>reset_n
This signal is the reset for primary mission-critical logic
<domain>reset_n_fdc
This signal is the reset for redundant logic
The GIC-600AE has an internal reset synchronizer, so that on reset the internal reset signal asserts
asynchronously and deasserts synchronously.
The functional requirements for the reset_n and reset_n_fdc signals are:
•
reset_n and reset_n_fdc must both assert before the reset can propagate to downstream logic.
If only one reset asserts, then GIC-600AE does not reset.
•
To ensure that reset can properly propagate through the primary and redundant logic pipelines,
the reset_n and reset_n_fdc signals must assert simultaneously for at least 16 clock cycles.
Otherwise, false fault assertions might occur.
The domain that contains the Distributor has separate dbg_[<domain>]reset_n and
dbg_[<domain>]reset_n_fdc signals. The dbg_* reset signals are used to reset debug, trace, and the
FMU error records containing fault status information. This functionality allows the GIC to be reset
using the reset_n and reset_n_fdc signals, while leaving any trace, debug, and fault error record
information available for later interrogation. It must be reset only when the [<domain>]reset_n and
[<domain>]reset_n_fdc signals are asserted.
6.5.2.1 DLS resetting
For blocks with Dual LockStep (DLS) logic, the redundant block must exit reset two cycles after the
primary block, or else false fault assertions occur.
The reset_sync_prot block guarantees this behavior for the main resets and the dbg_* reset
signals. It also filters out transient reset assertion by preventing reset from propagating unless the
reset_n and reset_n_fdc signals are both asserted.
The following figure shows this behavior in a timing diagram.
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