Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Functional Safety
Figure 6-6: FuSa reset timing diagram
reset_n_fdc
reset_n
clk
reset_n_sync
reset_n_fdc_sync
Filtering: Both resets must
be asserted to propagate
(asynchronous assertion).
Single reset must
be deasserted to
propagate
(synchronous
deassertion).
Logic guarantees
a temporal delay
of two cycles.
FuSa reset port fault protection
Transient reset port protection
The GIC protects the reset_n_sync, reset_n_fdc_sync, dbg_reset_n_sync, and
dbg_reset_n_fdc_sync signals from spurious transient faults. It does this in the
reset_sync_prot block by requiring both the primary and FDC resets to be asserted before
it asserts the synchronized reset to the downstream logic. For example, the reset_n_sync
and reset_n_fdc_sync signals are not asserted unless the reset_n and reset_n_fdc signals are
asserted at the same time.
Stuck-at-reset port protection/detection
The GIC protects itself from stuck-at-zero (STA0) faults on the reset pin inputs. Stuck-at-one
(STA1) faults are not detected or reported, as they prevent the GIC from resetting correctly.
If an implementation must detect STA1 faults, the SoC integrator can do so through external
hardware or self-test means. See Table 6-6: GIC reset failure modes on page 216 for more
information.
Internal reset fault protection/detection
The reset trees are duplicated, so faults on reset trees are detected through lockstep
protection mechanisms for the affected blocks.
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