ARM CoreLink GIC-600AE

Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Functional Safety
Figure 6-7: GIC reset protection
reset_n
nmbistreset
reset_n_fdc
nmbistreset_fdc
i_reset_n
i_reset_n_fdc
Reset Sync
Reset Sync
reset_n_sync
reset_n_fdc_sync
The following table describes the GIC reset failure modes.
Table 6-6: GIC reset failure modes
Signal Fault Detected
by GIC?
Failure mode
STA0
(asserted)
No GIC logic behaves normally. GIC prevents the reset_n signal from resetting GIC until the
reset_n_fdc signal is asserted.
reset_n
STA1 No GIC logic behaves normally. GIC cannot be reset.
STA0 No GIC logic behaves normally. GIC prevents the reset_n_fdc signal from resetting GIC until the
reset_n signal is asserted.
reset_n_fdc
STA1 No GIC logic behaves normally. GIC cannot be reset.
STA0 No PMU/FMU logic behaves normally. GIC prevents the dbg_reset_n signal from resetting DBG/
FMU until the dbg_reset_n_fdc signal is asserted.
dbg_reset_n
STA1 No PMU/FMU logic behaves normally. PMU/FMU cannot be reset.
STA0 No PMU/FMU logic behaves normally. GIC prevents the dbg_reset_n_fdc signal from resetting
DBG/FMU until the dbg_reset_n signal is asserted.
dbg_reset_n_fdc
STA1 No PMU/FMU logic behaves normally. PMU/FMU cannot be reset.
6.5.2.2 Cold reset sequence
Follow these steps to initiate a Cold reset of the GIC.
Procedure
1. Assert the reset_n_sync, reset_n_fdc_sync, dbg_reset_n_sync, and dbg_reset_n_fdc_sync signals
simultaneously.
•
reset_n_sync and reset_n_fdc_sync signals assert asynchronously at the same time. To
assert the reset_n_sync and reset_n_fdc_sync signals, both external ports must be asserted.
•
dbg_reset_n_sync and dbg_reset_n_fdc_sync signals assert asynchronously at the same
time. To assert the dbg_reset_n_sync and dbg_reset_n_fdc_sync signals, both external ports
must be asserted.
2. Keep the resets asserted for 16 clk cycles.
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