Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Operation
The ITS enables interrupts to be translated to the ID space of the hypervisor instead of directly to a
virtual machine.
Instead of using an ITS, registers can be used to configure the GIC-600AE to generate and control
LPIs. For more information, see GICR_SETLPIR register in the Arm
®
Generic Interrupt Controller
Architecture Specification, GIC architecture version 3 and version 4.
4.1.5 Choosing between LPIs and SPIs
Message-based interrupts can be either LPIs or SPIs.
The decision by software to use an LPI or SPI for an interrupt, depends on whether there are
message-based SPIs available and if the GIC-600AE has LPI support. The allocation of message-
based SPIs is set during the GIC configuration process. Also, if the hardware ensures that an spi
signal is held to a logic level that represents the inactive state, then software can use that SPI ID as
a message-based SPI.
The interrupt type can be selected by either making the peripheral write to a different GIC-600AE
address, or by changing the address translation for the interrupt write in the SMMU. Changing
only the SMMU is possible because the registers for Non-secure message-based interrupts,
GICD_SETSPI_NSR and GITS_TRANSLATER, or GICR_SETLPIR for configurations without ITS
support, are at the same address offset in different pages.
The following factors can help you to decide which interrupt type is most appropriate:
•
Only the ITS provides INTID translation, therefore LPIs are preferable for peripherals that a
virtual machine owns. This is because the hypervisor can let the virtual machine program the
peripheral directly, and the ITS converts the virtual machine interrupt IDs to unique physical
IDs.
•
LPIs are always Group 1 Non-secure, so message-based interrupts that target Secure software
must use SPIs.
•
Only SPIs are able to target all cores, which means that the GIC-600AE attempts to
automatically balance the interrupt load to cores that are active but not handling other
interrupts.
•
The GIC-600AE can provide more LPIs than SPIs.
•
You might decide not to include LPI support in a small system where the features of the ITS are
not required and there are few message-based interrupts.
•
SPIs usually have a better worst-case interrupt latency than LPIs. This difference is because
SPIs have all their settings stored internally to the GIC-600AE, whereas LPIs that are not
cached require external memory accesses. The cache hit rate is expected to be higher for the
LPIs that occur more frequently. Therefore, we recommend using SPIs for any latency-sensitive
interrupts that are expected to occur infrequently.
For more information, see the GICv3 and GICv4 Software Overview.
Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved.
Non-Confidential
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