ARM CoreLink GIC-600AE

Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Operation
Table 4-6: ECC error reporting
RAM Action in response to an uncorrectable error
ITS caches All ITS caches are memory that is backed. The contents are reloaded from memory. However, if entries are locked in the
errored cache line, the lock is lost. Software can use the GITS_OPSR register to determine if all expected locked entries are
still in place.
SPI The SPI is flagged as being in error and the error is reported through the GICD_ICERRRn register. The corrupted RAM
contents can be read until the error is cleared by writing to GICD_ICERRRn. SPIs that are in the error state can also be
determined by reading the GICD_ICERRRn register. This SPI is not reused until it is reprogrammed and re-enabled.
LPI All information from the RAM entry is reported. Software can determine the set of interrupts that might have errors, based
on the reported ID, to check priority, and to target information.
Note:
Repeated double errors in the LPI cache cause an overflow of the error record, which means subsequent information is
lost. We recommend that a high priority SPI is used to trigger a core, to clear the error record as fast as possible.
Redistributor
RAM
In the Redistributor, only group and priority are maintained in the RAM. If an error occurs, this information becomes
unknown for four interrupts. Pending and Active states are maintained but the enable is cleared so that the interrupt is not
forwarded.
You can determine the interrupts that are in error by reading the GICR_IERRVR register.
Note:
Because the group is unknown, it is assumed to be Secure, and so interrupt deactivates can be ignored. Software must
consider this as part of the recovery sequence.
It is also possible for a GenerateSGI packet to become corrupted. In this case, the GenerateSGI is reported as bad.
For more information about Pending and Active PPI states, see the GICv3 and GICv4 Software Overview.
SGI The SGI RAM holds group and Non-Secure Access Control (NSACR) information for all cores. It is used to enable wakeup of
the Redistributor as required. If an error occurs in the RAM, then all SGIs for that core are considered to be Secure. This
prevents Non-secure managers from raising Secure interrupts incorrectly.
4.15.5 Error recovery and fault handling interrupts
You can assign a recorded correctable ECC error to the fault handling interrupt by setting
GICT_ERR<n>CTLR.CFI.
All correctable ECC errors have error counters, so the interrupt only fires when the counter in the
associated GICT_ERR<n>MISC0 register overflows. You can preset the counter to any value by
writing to GICT_ERR<n>MISC0.Count. For example, to fire an interrupt on any correctable error,
write 0xFF, or to fire an interrupt on every second correctable error, write 0xFE.
You can assign a recorded uncorrectable ECC error either to the fault handling interrupt, fault_int
signal, by setting GICT_ERR<n>CTLR.FI, or to the error recovery interrupt, err_int signal, by setting
GICT_ERR<n>CTLR.UI. The interrupt fires on every uncorrectable interrupt occurrence irrespective
of the counter value.
You can route the fault_int and err_int signals out as interrupt wires for situations where error
recovery is handled by a core that does not receive interrupts directly from the GIC, such as
a central system control processor. Alternatively, you can drive each interrupt internally by
programming the associated GICT_ERRIRQCR<n> register.
Each GICT_ERRIRQCR<n> register contains an ID field that must be programmed to 0 if
internal routing is not required, or if internal routing is required, to a legally supported SPI ID.
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