Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Components and configuration
If the bypass switch is configured, it includes a transaction tracker that ensures PCIe ordering
requirements are met. There are two options that are based on the full_bypass_tracker
parameter:
0 A simple scheme is used, which ensures that all previous transactions sent
downstream have completed before forwarding an MSI to the ITS, and
conversely, that the ITS has accepted all MSIs before continuing to send traffic
downstream.
1 A more complex scheme, which allows continuous downstream traffic
including interleaved MSIs, unless the buffer slots become full. There are
two buffers, bypass_max_outstanding, which specifies the number of
concurrent downstream transactions allowed and bypass_interrupt_count,
which specifies the number of concurrent MSIs that can be waiting for their
prerequisite transactions to complete.
•
The ITS subordinate port contains only write-only registers, so the read channel
always uses a simple transaction tracker that only allows transactions to one
destination at a time.
•
If the bypass switch is configured, the subordinate and manager ports must both
have the same data width and the same address width.
•
If the Distributor and ITS both share the ACE-Lite subordinate port, the port
properties match those of the Distributor ACE-Lite subordinate port, which
3.1.2 Distributor ACE-Lite subordinate interface on page 27 describes.
The following table shows the acceptance capabilities of the ITS ACE-Lite subordinate interface.
Table 3-8: ITS ACE-Lite subordinate interface acceptance capabilities
Attribute With bypass switch Without bypass switch
Combined acceptance capability Read acceptance capability + Write acceptance capability 3
Read acceptance capability 128 1
Read data reorder depth 128 1
Write acceptance capability bypass_max_outstanding, but not exceeding 256 2
The ITS ACE-Lite subordinate interface has an associated awakeup signal. To ensure that incoming
traffic wakes the ITS correctly when it is clock gated hierarchically through the Q-Channel, the
awakeup signal must be driven from a registered version of the awvalid and arvalid signals. To
prevent spurious wake events, ensure that the awakeup signal is registered cleanly.
3.3.2 ITS ACE-Lite manager interface
The ITS AMBA
®
ACE-Lite manager interface has a configurable width of 64 bits, 128 bits, or 256
bits. If the bypass switch is not included, the ID width is 4 bits, otherwise the ID width is one more
than the ID width of the corresponding input channel.
The ACE-Lite manager port issues accesses to the ITS private tables and Command queue. If the
bypass switch is configured, the port also forwards transactions from the subordinate interface. The
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