Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Operation
4.16 Multichip operation
During silicon configuration, the system designers can configure the GIC-600AE to support
multichip operation.
Systems that comprise more than one chip, can have several SoCs that are connected externally or
an SoC comprising several SoCs connected inside a single physical package. In all cases, each SoC is
integrated with a GIC-600AE. A multichip system can have up to 16 chips.
To control the consistency of all chips in the configuration, and make the GIC appear as a single
entity to the OS, the GIC-600AE uses a set of registers that define the connectivity between chips.
These registers are referred to as the Routing table and consist of the following three register
types:
GICD_CHIPR<n>
These Chip Registers define the Routing table. It specifies the SPIs that the chip owns, and
how the chip is accessed. This register exists on each chip in the multichip configuration so
that each chip has a copy of the Routing table. The register number <n> corresponds to the
value of its chip_id signal.
GICD_DCHIPR
The Default Chip Register specifies the current chip that is responsible for the consistency of
the Routing table, and indicates when an update is in progress. A single copy of this register
exists on each chip in the multichip configuration.
GICD_CHIPSR
The Chip Status Register specifies details of the current status of the chip. A single copy of
this register exists on each chip in the multichip configuration.
At reset, each chip in the multichip system configuration is effectively a standalone full-featured
GIC. The GICD_CHIPSR register on the chip indicates this state with bit RTS == Disconnected.
For the multichip configuration to be fully coherent, all chips in the configuration must be
interconnected and one chip must own the Routing table.
The sequence for connecting chips together is described in 4.16.1 Connecting the chips on page
88.
When multiple chips in the configuration are connected, each set of 32 SPIs (SPI block) is owned by
a specific chip, so that the SPI space between chips is partitioned. Also:
•
SPIs that are not owned by any chip in accordance with the Routing table cannot be used.
•
SPI wires on a chip can only be used for SPIs that are owned. However, message-based
accesses to SPIs owned on any chip are supported.
•
The Routing table can only process one operation at a time. Therefore, software must
ensure that GICD_DCHIPR.PUP == 0 before commencing any operation such as writes to
GICD_CHIPRx or GICD_DCHIPR.
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