ARM CoreLink GIC-600AE

Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Programmers model
Usage constraints
Only accessible by Secure reads.
Bit descriptions
Figure 5-6: GICD_CHIPSR bit assignments
31 12 11 10 9 8 7 6 5 4 3 2 1
0
RTSReserved
SPI_busy Reserved
GTS
GTO
SGI_busy
LPI_busy
CC_busy Reserved
Reserved
Table 5-8: GICD_CHIPSR bit descriptions
Bits Name Description
[31:12] - Reserved, RES0
[11] SPI_busy
0 ongoing SPI-related cross-chip traffic
1 no traffic
[10] SGI_busy
0 ongoing SGI-related traffic or not all cores are asleep
1 no traffic
[9] LPI_busy
0 ongoing LPI-related traffic
1 no traffic
[8] CC_busy
0 ongoing cross-chip traffic
1 no traffic
[7:6] - Reserved, RES0
[5:4] RTS Routing table status:
0b00 disconnected
0b01 updating
0b10 consistent
0b11 Reserved
[3] - Reserved, RES0
[2] GTO Gating transaction ongoing:
0 no accesses
1 accesses ongoing
[1] GTS Gating status:
0 not gated
1 gated
[0] - Reserved, RES0
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