ARM CoreLink GIC-600AE

Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Programmers model
Bit descriptions
Figure 5-67: FMU_PINGNOW bit assignments
31 0
enable
1112 910 78
block_idReserved
ping_ack_received
remote_block_inject_error
gicd_inject_error
Table 5-81: FMU_PINGNOW bit descriptions
Bits Name Description
[31:12] - Reserved, RAZ
[11] remote_block_inject_error Set to 1 to inject an error on the PING_ACK response packet that is sent from the remote GIC block
to the FMU. This action causes errors along the route of the PING_ACK through the interconnect.
The presence of errors helps to confirm that the interconnect path from the specified remote GIC
block to the FMU has been properly connected.
[10] gicd_inject_error Set to 1 to inject an error on the PING data packet that is sent from the FMU to the remote GIC
block. This action causes errors along the route of the PING route through the interconnect. The
presence of errors helps to confirm that the interconnect path from the FMU to the specified remote
GIC block has been properly connected.
[9] ping_ack_received Indicates if a PING_ACK has been received:
0 PING_ACK has not been received
1 PING_ACK has been received from the GIC block that was pinged
[8] enable Ping enable:
0 Does not initiate a ping. Allows software to clear the status of this register without initiating
another ping.
1 Initiates a ping to the GIC block that FMU_PINGNOW.block_id specifies
[7:0] block_id Block identifier. Sends a ping request to the specified GIC block.
See Table 6-1: Error record block IDs on page 198 for block ID encodings.
5.10.8 FMU_SMEN, Safety Mechanism Enable register
This register enables or disables particular Safety Mechanisms inside a specified GIC block.
This feature cannot be used for the following FMU_SMEN field values:
•
BLK = GICD, SMID = 0
•
BLK = 3
•
BLK = PPI, SMID = 0
•
BLK = ITS, SMID = 0
•
BLK = SPI Collator, SMID = 0
•
BLK = Wake Request, SMID = 0
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