Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Programmers model
5.4.6 GICR_CLASSR, Class Register
This register specifies which class of 1 of N interrupt the CPU accepts.
Configurations
This register is available in all configurations.
Attributes
Width 32-bit
Functional group See 5.4 Redistributor registers for control and physical LPIs summary on page
121 for the address offset, type, and reset value of this register.
Usage constraints
Only accessible by Secure accesses.
Bit descriptions
Figure 5-24: GICR_CLASSR bit assignments
31 1 0
Reserved
Class
Table 5-28: GICR_CLASSR bit descriptions
Bits Name Description
[31:1] - Reserved, RAZ/WI
[0] Class Interrupt class:
0 Class 0
1 Class 1
5.4.7 GICR_PIDR2, Peripheral ID2 Register
This register returns byte[2] of the peripheral ID. The GICR_PIDR2 register is part of the set of
Redistributor peripheral identification registers.
Configurations
This register is available in all configurations.
Attributes
Width 32-bit
Functional group See 5.4 Redistributor registers for control and physical LPIs summary on page
121 for the address offset, type, and reset value of this register.
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