Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Programmers model
5.10.1 FMU_ERR<n>FR, Error Record Feature Register
This register defines which of the common architecturally-defined features are implemented and, of
the implemented features, which are software programmable.
Configurations
This register is available in all configurations.
Attributes
Width 64-bit
Functional group See 5.10 FMU register summary on page 179 for the address offset, type,
and reset value of this register.
Usage constraints
Only accessible by Secure accesses.
Bit descriptions
Figure 5-61: FMU_ERR<n>FR bit descriptions
EDReserved
Reserved
UIFI
8 5 34 12
Table 5-75: FMU_ERR<n>FR bit assignments
Bits Name Description
[63:8] - Reserved, RAZ
[7:6] FI Fault handling interrupt. Returns:
0b10 Fault handling interrupt is supported and controllable using FMU_ERR<n>CTLR.FI
[5:4] UI Error recovery interrupt for uncorrected errors. Returns:
0b10 Error recovery interrupt is supported and controllable using FMU_ERR<n>CTLR.UI
[3:2] - Reserved, RAZ
[1:0] ED Error reporting and logging. Returns:
0b10 Error reporting and logging is controllable using FMU_ERR<n>CTLR.ED
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