ARM CoreLink GIC-600AE

Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Programmers model
Bits Name Description Type Reset
[6] DS Disable Security RW Resets to:
•
0 when the
ds_value
configuration
parameter is
set to 0 or P
•
1 when
ds_value
is set to 1
[5] ARE_NS Affinity Routing Enable, Non-secure state RO 1
[4] ARE_S Affinity Routing Enable, Secure state RO 1
[3] - Reserved - -
[2] EnableGrp1S Enable Secure Group 1 interrupts RW 0
[1] EnableGrp1NS Enable Non-secure Group 1 interrupts RW 0
[0] EnableGrp0 Enable Group 0 interrupts RW 0
5.2.2 GICD_TYPER, Interrupt Controller Type Register
This register returns information about the configuration of the GIC-600AE. You can use this
register to determine the number of Security states, the number of INTIDs, and the number of
processor cores that the GIC supports.
Configurations
This register is available in all configurations.
Attributes
Width 32-bit
Functional group See 5.2 Distributor registers (GICD/GICDA) summary on page 98 for the
address offset, type, and reset value of this register.
Usage constraints
There are no usage constraints.
Bit descriptions
Figure 5-2: GICD_TYPER bit assignments
ITLinesNumber
31 27 26 25 24 23 19 18 17 16 15 11 10 9 8 7 5 4
0
CPU
Number
num_LPIsIDbitsReserved
Reserved
SecurityExtn
MBIS
LPIS
DVIS
A3V
No1N
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