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Explains what MBIST is and its role in testing embedded memories.
Details the interface between the MBIST controller and ATE/Cortex-A9.
Details the timing and operation modes of the MBIST controller.
Explains the MBIR structure, control unit, and dispatch unit fields.
Details specific fields within the MBIST Instruction Register (MBIR).
Explains what MBIST is and its role in testing embedded memories.
Details the interface between the MBIST controller and ATE/Cortex-A9.
Details the timing and operation modes of the MBIST controller.
Explains the MBIR structure, control unit, and dispatch unit fields.
Details specific fields within the MBIST Instruction Register (MBIR).
General| Architecture | ARMv7-A |
|---|---|
| Clock Speed | Up to 2 GHz |
| Memory Management Unit | Yes |
| TrustZone | Yes |
| Core Count | 1-4 |
| Instruction Set | ARM, Thumb-2 |
| Pipeline | 8-stage |
| Floating Point Unit | VFPv3 |
| NEON | Optional |
| L1 Cache | 32KB Instruction, 32KB Data, per core |
| MBIST | Built-in Memory BIST |
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