ARM Cortex-A9 MBIST User Manual

Functional Description
2-16 Copyright © 2008 ARM Limited. All rights reserved. ARM DDI 0414C
Non-Confidential
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Starting MBIST
After loading the MBIST instruction, drive MBISTSHIFT LOW and disable CLK.
With CLK disabled, drive MBISTRUN HIGH and, after an MBISTRUN setup time,
start the PLL at the test frequency as shown in Figure 2-16.
Figure 2-16 Starting the MBIST test
Failure detection
The MBISTRESULT[1] flag goes HIGH two CLK cycles after the controller detects
a failure, as Figure 2-17 shows. It stays HIGH if sticky fail is enabled. If stop-on-fail is
enabled, the MBISTRESULT[0] flag goes HIGH two cycles later.
Figure 2-17 Detecting an MBIST failure
Note
To ensure that the ATE can observe a failure at test speed, specify a sticky fail in the
MBIST instruction. See Control field, MBIR[51:46] on page 3-7.
Data log retrieval
During a test, the MBIST controller automatically logs the first detected failure. If
required, you can retrieve the data log at the end of the test to generate failure statistics.
Figure 2-18 on page 2-17 and Figure 2-19 on page 2-17 show the method of retrieving
a data log.
Note
MBISTRESULT[2] is the serial data output for instructions and the data log for CPU0.
CLK
MBISTRUN
MBISTSHIFT
With stop-on-fail enabled and
only one cycle of latency
With sticky fail enabled
CLK
MBISTRESULT[1] (fail flag)
MBISTRESULT[0] (complete flag)

ARM Cortex-A9 MBIST Specifications

General

Architecture	ARMv7-A
Clock Speed	Up to 2 GHz
Memory Management Unit	Yes
TrustZone	Yes
Core Count	1-4
Instruction Set	ARM, Thumb-2
Pipeline	8-stage
Floating Point Unit	VFPv3
NEON	Optional
L1 Cache	32KB Instruction, 32KB Data, per core
MBIST	Built-in Memory BIST