ARM Cortex-A9 MBIST User Manual

ARM DDI 0414C Copyright © 2008 ARM Limited. All rights reserved. B-1
Restricted Access Non-Confidential
Appendix B
Revisions
This appendix describes the technical changes between released issues of this book.
Table B-1 Differences between issue A and issue B
Change Location
No technical changes -
Table B-2 Differences between issue B and issue C
Change Location
Updated description about the MBIST controller About the MBIST controller on page 1-2
Updated MBIST controller signals Figure 1-2 on page 1-3
Updated MBIST controller interface signals Figure 1-3 on page 1-4
Updated signal names and settings Table 2-1 on page 2-2
Updated bit information for the MBIST controller interfaces Table 2-2 on page 2-2
Clarified data in for Instruction tag RAM Figure 2-3 on page 2-6

ARM Cortex-A9 MBIST Specifications

General

Architecture	ARMv7-A
Clock Speed	Up to 2 GHz
Memory Management Unit	Yes
TrustZone	Yes
Core Count	1-4
Instruction Set	ARM, Thumb-2
Pipeline	8-stage
Floating Point Unit	VFPv3
NEON	Optional
L1 Cache	32KB Instruction, 32KB Data, per core
MBIST	Built-in Memory BIST