ARM Cortex-A9 MBIST User Manual

MBIST Instruction Register
ARM DDI 0414C Copyright © 2008 ARM Limited. All rights reserved. 3-9
Restricted Access Non-Confidential
Setting one of the MBIR[36:39] bits to 0 disables the data comparison for the relevant
CPU. Table 3-6 shows the CPU mapping of this field.MBIR
3.2.5 MaxXAddr and MaxYAddr fields, MBIR[35:32] and MBIR[31:28]
You can determine the number of address bits you must specify for a RAM from the
MBIR fields:
• MaxXAddr on page 3-10
• MaxYAddr on page 3-10.
This enables you to specify your address range in two dimensions. The two-dimensional
specification represents the topology of the physical implementation of the RAM more
accurately. The dimensions are controlled by two separate address counters, the
X-address counter and the Y-address counter. One counter can be incremented or
decremented only when the other counter has expired. The chosen test algorithm
determines the counter that moves faster.
Use this procedure to determine how many bits to assign to the X-address and Y-address
counters:
1. Determine the column width of the RAM array. The Y-address must have at least
that many bits for the column select.
2. Determine how many address bits the RAM requires. See the Cortex-A9
Processor Configuration and Sign-off Guide for more information.
Table 3-6 MBIR[39:36] CPU mapping
MBIR bit CPU
36 CPU0
37 CPU1
38 CPU2
39 CPU3

ARM Cortex-A9 MBIST Specifications

General

Architecture	ARMv7-A
Clock Speed	Up to 2 GHz
Memory Management Unit	Yes
TrustZone	Yes
Core Count	1-4
Instruction Set	ARM, Thumb-2
Pipeline	8-stage
Floating Point Unit	VFPv3
NEON	Optional
L1 Cache	32KB Instruction, 32KB Data, per core
MBIST	Built-in Memory BIST