ARM Cortex-A9 MBIST User Manual

Introduction
1-4 Copyright © 2008 ARM Limited. All rights reserved. ARM DDI 0414C
Non-Confidential
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Figure 1-3 Traditional method of interfacing MBIST
Because this method significantly reduces the maximum operating frequency, it is not
suitable for high-performance designs. Instead, the MBIST controller uses an additional
input to the existing functional multiplexors without reducing maximum operating
frequency.
Figure 1-4 on page 1-5 shows the six pipeline stages used to access the RAM arrays.
DataIn
BistDataIn
0
1
0
1
Address
BistAddress
0
1
CE
BistCE
0
1
WE
BistWE
BistMode
RAM
DataOut
BistDataOut

ARM Cortex-A9 MBIST Specifications

General

Architecture	ARMv7-A
Clock Speed	Up to 2 GHz
Memory Management Unit	Yes
TrustZone	Yes
Core Count	1-4
Instruction Set	ARM, Thumb-2
Pipeline	8-stage
Floating Point Unit	VFPv3
NEON	Optional
L1 Cache	32KB Instruction, 32KB Data, per core
MBIST	Built-in Memory BIST