Functional Description
ARM DDI 0414C Copyright © 2008 ARM Limited. All rights reserved. 2-13
Restricted Access Non-Confidential
MBIST controller block top level I/O
The top level I/O of the MBIST controller contains the Cortex-A9 processor interface.
See Appendix A Signal Descriptions and the inputs and outputs shown in Table 2-8.
Note
The reset signals of the Cortex-A9 processor must be HIGH in MBIST test mode.
Because the MBIST test mode uses some functional paths to access RAMs, the registers
on those paths have to be out of reset.
The following signals have additional information:
SE Preservation of array state is required when performing multiload
Automatic Test Pattern Generator (ATPG) runs or when performing
IDDQ testing. After performing MBIST tests to initialize the arrays to a
required background, the ATPG test procedures must assert SE during all
test setup cycles in addition to load/unload. Any clocking during IDDQ
capture cycles must have array chip select signals constrained.
MBISTRESULT[5:0]
During tests, the MBISTRESULT[1] signal indicates failures. You can
operate using two modes, by configuring bit [5] of the engine control
section of the instruction register. If bit [5] is set, the MBISTRESULT[1]
Table 2-8 MBIST controller top level I/O
Signal Direction Function Value, MBIST mode Value, function mode
MBISTDATAIN Input Serial data in Toggle 0
MBISTDSHIFT Input Data log shift Toggle 0
nRESET Input MBIST reset Toggle
0
a
MBISTRESULT[5:0] Output Output status bus Strobe -
MBISTRUN Input Run MBIST test Toggle 0
MBISTSHIFT Input Instruction shift Toggle 0
MBISTENABLE Input MBIST path enable Toggle 0
SE Input ATPG signal 0 0
a. nRESET and MBISTENABLE must be LOW in functional mode.
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