ARM Cortex-A9 MBIST User Manual

Functional Description
2-14 Copyright © 2008 ARM Limited. All rights reserved. ARM DDI 0414C
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signal is asserted for a single cycle for each failed compare. If bit [5] is
not set, the MBISTRESULT[1] signal is sticky, and is asserted from the
first failure until the end of the test.
At the completion of the test, the MBISTRESULT[0] signal goes HIGH.
The MBISTRESULT[5:2] signal indicates that an address expire for
CPU0 has occurred and enables you to measure sequential progress
through the test algorithms.

ARM Cortex-A9 MBIST Specifications

General

Architecture	ARMv7-A
Clock Speed	Up to 2 GHz
Memory Management Unit	Yes
TrustZone	Yes
Core Count	1-4
Instruction Set	ARM, Thumb-2
Pipeline	8-stage
Floating Point Unit	VFPv3
NEON	Optional
L1 Cache	32KB Instruction, 32KB Data, per core
MBIST	Built-in Memory BIST