ARM Cortex-A9 MBIST User Manual

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Chapter 3

MBIST Instruction Register

This chapter describes how to use the MBIST Instruction Register (MBIR) to configure

the mode of operation of the MBIST controller. It contains the following sections:

• About the MBIST instruction register on page 3-2

• Field descriptions on page 3-4.

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General

Architecture	ARMv7-A
Clock Speed	Up to 2 GHz
Memory Management Unit	Yes
TrustZone	Yes
Core Count	1-4
Instruction Set	ARM, Thumb-2
Pipeline	8-stage
Floating Point Unit	VFPv3
NEON	Optional
L1 Cache	32KB Instruction, 32KB Data, per core
MBIST	Built-in Memory BIST