ARM Cortex-A9 MBIST User Manual

Functional Description
2-12 Copyright © 2008 ARM Limited. All rights reserved. ARM DDI 0414C
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When the instruction shift is enabled, data shifts between the two parts of
the BIST engine are on bit 3. In run test mode, this bit is used as invert
data information. The MBISTTX[11:0] interface is ARM-specific and
intended for use only with the MBIST controller.
MBISTRX[5:0]
This signal is an output of the dispatch unit that goes to the MBIST
controller. The behavior of MBISTRX[5:0] is ARM-specific and is
intended for use only with the MBIST controller. The address expire
signal is set when both the row and column address counters expire.
Table 2-7 shows the signals.
9 Enable bitmap mode
10 Increment go/nogo dataword selection
11 Latency stall control
Table 2-7 MBISTRX signals
MBISTRX bit Description
0 Real-time error flag
1 Shadow pipeline empty
2 CPU0 address/instruction data out/fail data out
3 CPU1 address/instruction data out/fail data out
4 CPU2 address/instruction data out/fail data out
5 CPU3 address/instruction data out/fail data out
Table 2-6 MBISTTX signals (continued)
MBISTTX bit Description

ARM Cortex-A9 MBIST Specifications

General

Architecture	ARMv7-A
Clock Speed	Up to 2 GHz
Memory Management Unit	Yes
TrustZone	Yes
Core Count	1-4
Instruction Set	ARM, Thumb-2
Pipeline	8-stage
Floating Point Unit	VFPv3
NEON	Optional
L1 Cache	32KB Instruction, 32KB Data, per core
MBIST	Built-in Memory BIST