ARM Cortex-A9 MBIST User Manual

Functional Description
ARM DDI 0414C Copyright © 2008 ARM Limited. All rights reserved. 2-7
Restricted Access Non-Confidential
Figure 2-4 Data out for Instruction tag RAM
Figure 2-5 and Figure 2-6 show the data mapping on MBISTINDATA and
MBISTOUTDATA buses for Data tag RAM and SCU tag RAM.
Figure 2-5 Data in for Data tag RAM and SCU tag RAM
Figure 2-6 Data out for Data tag RAM and SCU tag RAM
63 0127128191192255 64
Data out
[21:0]
for array
n+1
Data out
[21:0]
for array n
Data out
[21:0]
for array
n+1
Data out
[21:0]
for array n
Data out
[21:0]
for array
n+1
Data out
[21:0]
for array n
Data out
[21:0]
for array
n+1
Data out
[21:0]
for array n
Data out [63:0] for CPU 3 Data out [63:0] for CPU 2 Data out [63:0] for CPU 1 Data out [63:0] for CPU 0
Unused
MBISTINDATA[63:0]
Data in [25:0] for array n
Unused
3132 0575863 2526
MBISTOUTDATA[255:0]
63 0127128191192255 64
Data out
[25:0]
for array
n+1
Data out
[25:0]
for array n
Data out
[25:0]
for array
n+1
Data out
[25:0]
for array n
Data out
[25:0]
for array
n+1
Data out
[25:0]
for array n
Data out
[25:0]
for array
n+1
Data out
[25:0]
for array n
Data out [63:0] for CPU3 Data out [63:0] for CPU2 Data out [63:0] for CPU1 Data out [63:0] for CPU0
Unused

ARM Cortex-A9 MBIST Specifications

General

Architecture	ARMv7-A
Clock Speed	Up to 2 GHz
Memory Management Unit	Yes
TrustZone	Yes
Core Count	1-4
Instruction Set	ARM, Thumb-2
Pipeline	8-stage
Floating Point Unit	VFPv3
NEON	Optional
L1 Cache	32KB Instruction, 32KB Data, per core
MBIST	Built-in Memory BIST