ARM Cortex-A9 MBIST User Manual

MBIST Instruction Register
3-8 Copyright © 2008 ARM Limited. All rights reserved. ARM DDI 0414C
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Table 3-4 shows the latency settings for read operations.
Table 3-5 shows the latency settings for write operations.
3.2.4 CPU On field, MBIR[39:36]
The CPU On field controls data comparison for the CPUs under test.
Table 3-4 Read latency field encoding
Read Latency MBIR[42:40] Number of cycles per read operation
b000 1
b001 2
b010 3
b011 4
b100 5
b101 6
b110 7
b111 8
Table 3-5 Write latency field encoding
Write Latency MBIR[45:43] Number of cycles per write operation
b000 1
b001 2
b010 3
b011 4
b100 5
b101 6
b110 7
b111 8

ARM Cortex-A9 MBIST Specifications

General

Architecture	ARMv7-A
Clock Speed	Up to 2 GHz
Memory Management Unit	Yes
TrustZone	Yes
Core Count	1-4
Instruction Set	ARM, Thumb-2
Pipeline	8-stage
Floating Point Unit	VFPv3
NEON	Optional
L1 Cache	32KB Instruction, 32KB Data, per core
MBIST	Built-in Memory BIST