ARM Cortex-A9 MBIST User Manual

Signal Descriptions
A-4 Copyright © 2008 ARM Limited. All rights reserved. ARM DDI 0414C
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A.2 Miscellaneous signals
Table A-3 shows the miscellaneous signals.
Table A-3 Miscellaneous signals
Signal Type Description
nRESET Input Global active LOW reset signal
CLK Input Clock
MBISTDATAIN Input Serial data in
MBISTDSHIFT Input Data log shift
MBISTRESETN Input MBIST reset
MBISTRESULT[5:0] Output Output status bus
MBISTRUN Input Run MBIST test
MBISTSHIFT Input Instruction shift
MBISTENABLE Input MBIST mode enable

ARM Cortex-A9 MBIST Specifications

General

Architecture	ARMv7-A
Clock Speed	Up to 2 GHz
Memory Management Unit	Yes
TrustZone	Yes
Core Count	1-4
Instruction Set	ARM, Thumb-2
Pipeline	8-stage
Floating Point Unit	VFPv3
NEON	Optional
L1 Cache	32KB Instruction, 32KB Data, per core
MBIST	Built-in Memory BIST