ARM Cortex-A9 MBIST User Manual

Functional Description
ARM DDI 0414C Copyright © 2008 ARM Limited. All rights reserved. 2-17
Restricted Access Non-Confidential
MBISTRESULT[3] is the serial data output for instructions and the data log for CPU1.
MBISTRESULT[4] is the serial data output for instructions and the data log for CPU2.
MBISTRESULT[5] is the serial data output for instructions and the data log for CPU3.
After the MBISTRESULT[1] flag goes HIGH, stop the test by putting the PLL in
bypass mode and driving MBISTRUN LOW as Figure 2-18 shows. To begin shifting
out the data log on MBISTRESULT[5:2], drive MBISTDSHIFT HIGH. The
MBISTRESULT[1] flag goes LOW two cycles after MBISTRUN goes LOW. Data
begins shifting out on MBISTRESULT[5:2] two cycles after MBISTDSHIFT goes
HIGH.
Figure 2-18 Start of data log retrieval
When the last data log bit shifts out, drive MBISTDSHIFT LOW as Figure 2-19 shows.
Figure 2-19 End of data log retrieval
CLK
MBISTRESULT[2]
(complete flag)
MBISTDSHIFT
MBISTRESULT[5:2]
(data log shift out)
MBISTRUN
D[0]
MBISTRESULT[2]
MBISTDSHIFT
MBISTRESULT[5:2]
MBISTRUN
D[78]D[77]D[76]
CLK

ARM Cortex-A9 MBIST Specifications

General

Architecture	ARMv7-A
Clock Speed	Up to 2 GHz
Memory Management Unit	Yes
TrustZone	Yes
Core Count	1-4
Instruction Set	ARM, Thumb-2
Pipeline	8-stage
Floating Point Unit	VFPv3
NEON	Optional
L1 Cache	32KB Instruction, 32KB Data, per core
MBIST	Built-in Memory BIST