ARM Cortex-A9 MBIST User Manual

Revisions
B-2 Copyright © 2008 ARM Limited. All rights reserved. ARM DDI 0414C
Non-Confidential
Restricted Access
Clarified data out for Instruction tag RAM Figure 2-4 on page 2-7
Clarified Tag RAM control Table 2-5 on page 2-8
Updated TLB RAM description TLB RAM on page 2-9
Updated Branch Target Address Cache RAM description Branch Target Address Cache RAM on page 2-8
Table B-2 Differences between issue B and issue C (continued)
Change Location

ARM Cortex-A9 MBIST Specifications

General

Architecture	ARMv7-A
Clock Speed	Up to 2 GHz
Memory Management Unit	Yes
TrustZone	Yes
Core Count	1-4
Instruction Set	ARM, Thumb-2
Pipeline	8-stage
Floating Point Unit	VFPv3
NEON	Optional
L1 Cache	32KB Instruction, 32KB Data, per core
MBIST	Built-in Memory BIST