ARM Cortex-A9 MBIST User Manual

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Glossary
This glossary describes some of the terms used in technical documents from ARM
Limited.
Block address An address that comprises a tag, an index, and a word field. The tag bits identify the way
that contains the matching cache entry for a cache hit. The index bits identify the set
being addressed. The word field contains the word address that can be used to identify
specific words, halfwords, or bytes within the cache entry.
See also Cache terminology diagram on the last page of this glossary.
Byte An 8-bit data item.
Cache A block of on-chip or off-chip fast access memory locations, situated between the
Cortex-A9 processor and main memory, used for storing and retrieving copies of often
used instructions and/or data. This is done to greatly increase the average speed of
memory accesses and so improve Cortex-A9 processor performance.
See also Cache terminology diagram on the last page of this glossary.
Cache line The basic unit of storage in a cache. It is always a power of two words in size (usually
four or eight words), and is required to be aligned to a suitable memory boundary.
See also Cache terminology diagram on the last page of this glossary.

ARM Cortex-A9 MBIST Specifications

General

Architecture	ARMv7-A
Clock Speed	Up to 2 GHz
Memory Management Unit	Yes
TrustZone	Yes
Core Count	1-4
Instruction Set	ARM, Thumb-2
Pipeline	8-stage
Floating Point Unit	VFPv3
NEON	Optional
L1 Cache	32KB Instruction, 32KB Data, per core
MBIST	Built-in Memory BIST