Glossary
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Cache miss A memory access that cannot be processed at high speed because the instruction/data it
addresses is not in the cache and a main memory access is required.
Core A core is that part of a Cortex-A9 processor that contains the ALU, the datapath, the
general-purpose registers, the Program Counter, and the instruction decode and control
circuitry.
Data cache A block of on-chip fast access memory locations, situated between the Cortex-A9
processor and main memory, used for storing and retrieving copies of often used data.
This is done to greatly increase the average speed of memory accesses and so improve
Cortex-A9 processor performance.
Halfword A 16-bit data item.
Instruction cache A block of on-chip fast access memory locations, situated between the Cortex-A9
processor and main memory, used for storing and retrieving copies of often used
instructions. This is done to greatly increase the average speed of memory accesses and
so improve Cortex-A9 processor performance.
Tag The upper portion of a block address used to identify a cache line within a cache. The
block address from the CPU is compared with each tag in a set in parallel to determine
if the corresponding line is in the cache. If it is, it is said to be a cache hit and the line
can be fetched from cache. If the block address does not correspond to any of the tags,
it is said to be a cache miss and the line must be fetched from the next level of memory.
See also Cache terminology diagram on the last page of this glossary.
TLB See Translation Look-aside Buffer.
Translation Lookaside Buffer (TLB)
A cache of recently used page table entries that avoid the overhead of page table
walking on every memory access. Part of the Memory Management Unit.
Word A 32-bit data item.
Cache terminology diagram
The diagram illustrates the following cache terminology:
• block address
• cache line
• cache set
• cache way
•index
•tag.
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