Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Programmers model
Bit descriptions
Figure 5-21: GICR_WAKER bit assignments
31 30 3 2 1
0
ChildrenAsleepQuiescent
Reserved
ProcessorSleep
Sleep
Table 5-25: GICR_WAKER bit descriptions
Bits Name Description
[31] Quiescent Indicates that the GIC-600AE is idle and can be powered down if necessary
[30:3] - Reserved, RAZ
[2] ChildrenAsleep Indicates that the bus between the CPU interface and this Redistributor is quiescent
[1] ProcessorSleep Indicates:
0 This Redistributor never asserts a wake_request signal and it delivers the interrupt to the core
1 This Redistributor must assert a wake_request signal if there is a pending interrupt targeted at the
connected core. See 4.6.2 Processor core power management on page 57.
[0] Sleep Indicates the sleep state:
0 Normal operation
1 The GIC-600AE ensures that all the caches are consistent with external memory and that it is safe to
power down. See 4.6.3 Other power management on page 58.
5.4.4 GICR_FCTLR, Function Control Register
This register controls the scrubbing of all RAMs in the associated Redistributor.
Configurations
This register is available in all configurations.
Attributes
Width 32-bit
Functional group See 5.4 Redistributor registers for control and physical LPIs summary on page
121 for the address offset, type, and reset value of this register.
Usage constraints
There are no usage constraints.
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