Arm
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CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Programmers model
Table 5-40: GITS_OPR bit descriptions
Bits Name Description
[63:60] LOCK_TYPE Lock type supported:
0 Track
1 Trial
2 ITS lock
3 ITS unlock
4 Track abort
8 ITS unlock all
5‑7, 9‑15 Reserved
Note:
•
If GITS_OPSR.REQUEST_IN_PROGRESS == 1, when attempting a new access (other than
Track abort (4) during a Track) the behavior is unpredictable.
•
Invalidating the VCACHE by using GITS_FCTLR.XXX unlocks all the locked entries.
However, if a GITS_OPR lock request occurs while an invalidation is in progress
(GITS_FCTLR.XXX == 1), then it is unpredictable whether the entries remain locked when
the invalidation completes. This unpredictable behavior might cause GITS_OPSR to return
an incorrect status.
[59:52] - Reserved, RES0
[51:32] DEVICE_ID Sets the DeviceID. The number of bits that are implemented in this field is configuration
dependent. To determine the width of this field, software can read GITS_TYPER.DevBits.
[31:16] - Reserved, RES0
[15:0] EVENT_ID Sets the EventID. The number of bits that are implemented in this field is configuration
dependent. To determine the width of this field, software can read GITS_TYPER.IDBits.
5.6.5 GITS_OPSR, Operation Status Register
This register indicates cache lock status.
Configurations
This register is available in all configurations that have one or more ITS blocks.
Attributes
Width 64-bit
Functional group See 5.6 ITS control register summary on page 136 for the address offset,
type, and reset value of this register.
Usage constraints
There are no usage constraints.
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