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Arm

CoreLink™ GIC-600AE Generic Interrupt Controller

Technical Reference Manual

Document ID: 101206_0003_04_en

Issue: 04

Operation

4.15.1 Non-secure access

You can control whether Non-secure software has access to the RAS architecture-compliant

the GICTNS bit.

If there is an error, and if GICD_CTLR.DS == 0, all SPIs, PPIs, and SGIs resort to a Secure group.

Therefore, interrupt programming is not revealed to the Non-secure side.

4.15.2 Scrub

The GIC-600AE holds signiﬁcant programming and interrupt states in RAM, which is protected by

Single Error Correction and Double Error Detection (SECDED).

However, some RAM content might be static for a long duration, and there is a potential for

errors to accumulate if a particular address is not periodically accessed. To prevent this occurring,

software can periodically trigger a low-priority scrub of a RAM, by setting the GITS_FCTLR.SIP,

GICR_FCTLR.SIP, and GICD_FCTLR.SIP bits. This process triggers a check and if necessary, a write-

back of all valid RAM entries. Any errors that are found during a scrub are also reported in the

relevant RAS error record.

4.15.3 Error record classiﬁcation

The GIC reports errors in Armv8.2 RAS architecture-compliant error records, which are accessible

through the ACE-Lite subordinate programming interface.

The classes of error records are:

•

Correctable ECC errors

•

Uncorrectable ECC errors

•

ITS command and translation errors

•

Software access errors

The error records have a separate reset so that they can be read after a main GIC reset to

determine any problems.

4.15.4 ECC error reporting and recovery

When an ECC error is detected, the GIC-600AE attempts to contain the error and ensure it cannot

propagate further.

The following table shows the GIC behavior when errors are detected in each RAM.

Non-Conﬁdential

Page 69 of 268

ARM CoreLink GIC-600AE User Manual

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