ARM CoreLink GIC-600AE User Manual

Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Programmers model
Bit descriptions
Figure 5-33: GITS_OPSR bit assignments
63 48 32
TARGETReserved
45474962
61 60
31 16 15 0
PIDReserved
44
Reserved
ENTRY_LOCKEDREQUEST_IN_PROGRESS
REQUEST_PASS
REQUEST_COMPLETE
Table 5-41: GITS_OPSR bit descriptions
Bits Name Description
[63] REQUEST_COMPLETE Request to GITS_OPR completed
[62] REQUEST_PASS Request to GITS_OPR completed without error
[61] REQUEST_IN_PROGRESS Request to GITS_OPR in progress
[60:49] - Reserved, RES0
[48] ENTRY_LOCKED Locked entry in cache corresponds to request (valid for trial and lock operations)
[47:45] - Reserved, RES0
[44:32] TARGET Target of interrupt requested. Valid for trial and lock operations.
[31:16] - Reserved, RES0
[15:0] PID Physical ID of interrupt requested (valid for trial and lock operations)
5.6.6 GITS_CFGID, Configuration ID Register
This register returns information about the configuration of the ITS block such as its ID number.
Configurations
This register is available in all configurations that have one or more ITS blocks.
Attributes
Width 32-bit
Functional group See 5.6 ITS control register summary on page 136 for the address offset,
type, and reset value of this register.
Usage constraints
There are no usage constraints.
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ARM CoreLink GIC-600AE Specifications

General

Brand	ARM
Model	CoreLink GIC-600AE
Category	Controller
Language	English