ARM CoreLink GIC-600AE User Manual

Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Operation
aff0_
thread == 0
The four fields map to 0.0.<cluster>.<core>
See the Arm
®
CoreLink
™
GIC-600AE Generic Interrupt Controller Configuration and Integration Manual
for information about the aff0_thread configuration parameter and how to build affinity schemes
that include heterogenous clusters and multithreaded cores.
The following figure shows the affinity hierarchical structure.
Figure 4-1: Affinity routing
Distributor
0
CPU
interface
0.x.x.x
0.0.0.x
0.255.x.x
0.255.0.x
…..
…..
0
0
CPU
interface
CPU
interface
CPU
interface
CPU
interface
CPU
interface
…..
0.0.255.x
…..
Aff Level 3
Aff Level 2
…..…..
Aff Level 1
0.0.x.x
Aff Level 0
Redistributor
0.255.0.150.255.0.00.0.255.150.0.255.00.0.0.0
0.0.0.15
…..
15
15
15
There can be up to 256 nodes at level 3, with each node able to host 256 child level 2 nodes.
Similarly each level 2 node can host 256 level 1 nodes. However, level 1 nodes can only host 16
child level 0 nodes.
For more information about affinity routing, see the GICv3 and GICv4 Software Overview and
the Arm
®
Generic Interrupt Controller Architecture Specification, GIC architecture version 3 and
version 4.
4.5 SPI routing and 1 of N selection
The GIC-600AE supports 1 of N selection of SPI interrupts. You can program an SPI to target
several cores, and the GIC-600AE can select which cores receive an SPI.
When the relevant GICD_IROUTERn.Interrupt_Routing_Mode == 1, the GIC selects an appropriate
core for an SPI.
When GICD_IROUTERn.Interrupt_Routing_Mode == 0, the SPI is routed to the core specified by
the remaining fields of GICD_IROUTERn.
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ARM CoreLink GIC-600AE Specifications

General

Brand	ARM
Model	CoreLink GIC-600AE
Category	Controller
Language	English