Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Operation
The GIC-600AE only sends an SPI to cores that are powered up and have the relevant interrupt
group enabled. The GIC-600AE prioritizes cores that are considered active, but if there are no
active cores, it selects inactive cores.
The selections that the GIC-600AE makes can be controlled or influenced by several 1 of N
features:
cpu_active signal
A cpu_active signal is an input to a Redistributor that corresponds to a particular core. When
a cpu_active signal is LOW, it indicates to the GIC that a core is in a transparent low-power
state such as retention, and that it must be selected as a target for an SPI if there are no
other options possible.
Ideally, the cores that are in retention are not woken without explicit software intervention,
so that cores spend more time in retention. To ensure that this behavior is usually the case,
use the following guidelines:
•
Cores in retention must drive their corresponding cpu_active signal LOW.
•
Powered-up cores that are not in retention must drive their cpu_active signal HIGH.
Typically, a power controller or power control logic generates the cpu_active signal. If this
signal is not available in the system, the input must be tied HIGH.
•
When a core is powered down, the value of its cpu_active signal is
irrelevant. This irrelevancy is because the software programming
requirements for the GIC ensure that it knows when cores are powered
up or down.
•
The cpu_active signal provides an indication only, it cannot stop selection
of the core or stop the GIC sending messages to the core.
GICR_CTLR.DPGxx (Disabled Processor Group)
Setting a DPG bit prevents 1 of N interrupts of a particular group being sent to that core.
Any interrupts that have not reached a core at the time of the change, are recalled and
reprioritized by the GIC.
Processor and GICD group enables and GICR_WAKER.ProcessorSleep
A 1 of N interrupt is not sent to a core if one of the following is true:
•
The core is asleep, as indicated by GICR_WAKER.ProcessorSleep.
•
The interrupt group is disabled by either the processor or the GICD_CTLR group enables.
Interrupt class
This is an implementation-defined feature that the GIC-600AE provides. Each core can be
assigned to either class 0 or class 1 by writing to the relevant GICR_CLASSR register. An SPI,
programmed as 1 of N, by GICD_IROUTERn.Interrupt_Routing_Mode, can be programmed to
target either class 0, class 1, or both classes by the GICD_ICLARn register. By default, all 1 of
N SPIs can go to both classes, so the interrupt class feature is disabled by default. The system
can use this partitioning for any purpose, for example in an Arm
®
big.LITTLE
™
system, all the
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