Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Programmers model
Attributes
Width 64-bit
Functional group See 5.2 Distributor registers (GICD/GICDA) summary on page 98 for the
address offset, type, and reset value of this register.
Usage constraints
Only accessible by Secure accesses.
Ignores writes if any interrupt group enable is set, that is, GICD_CTLR.EnableGrp0 == 1, or
EnableGrp1NS == 1, or EnableGrp1S == 1.
Bit descriptions
Figure 5-8: GICD_CHIPR<n> bit assignments
16 15 10 9 5 4 2 1 0
SPI_BLOCKS
48
ADDR
63
Reserved
47
Reserved
PUP
SocketState
SPI_BLOCK_MINADDR
32
31
Table 5-10: GICD_CHIPR<n> bit assignments
Bits Name Description Type
[63:48] - Reserved -
[47:16] ADDR Controls the value of the icdrtdest signal, when routing messages to the remote chip. The
chip_addr_width configuration parameter controls the width of this field, so the field spans from
bit[16] upwards.
RW
[15:10] SPI_BLOCK_MIN Controls the minimum number of SPIs in a group (block). The permitted values are 0-31. RW
[9:5] SPI_BLOCKS Controls the number of SPI blocks. The permitted values are 0-31. RW
[4:2] - Reserved -
[1] PUP This bit returns the power update status:
0 Power update complete
1 Power update in progress
RO
[0] SocketState This bit controls the state of the chip:
0 Chip is offline
1 Chip is online
RW
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