Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Programmers model
Bit descriptions
Figure 5-5: GICD_SAC bit assignments
31 3 2 1 0
Reserved
GICPNS
GICTNS
DSL
Table 5-7: GICD_SAC bit assignments
Bits Name Description Type
[31:3] - Reserved, returns zero -
[2] GICPNS Controls whether the Non-secure world can access the Secure PMU data:
0 Secure access only
1 Allow Non-secure access to the GICP registers
The gicp_allow_ns tie-off signal controls the reset value on a per-chip basis.
RW
[1] GICTNS Controls whether the Non-secure world can access the Secure trace data:
0 Secure access only
1 Allow Non-secure access to the GICT registers
The gict_allow_ns tie-off signal controls the reset value on a per-chip basis.
RW
[0] DSL Disable security lock. WriteOnce (WO):
0 No effect
1 WO bit to lock GICD_CTLR.DS to be WO at its current value
When set to 1, this bit only returns to 0 when the GIC is reset.
RW
5.2.6 GICD_CHIPSR, Chip Status Register
This register returns the status of the chip in a multichip configuration. A single copy of this register
exists on each chip in a multichip configuration.
Configurations
This register is available in all multichip configurations.
Attributes
Width 32-bit
Functional group See 5.2 Distributor registers (GICD/GICDA) summary on page 98 for the
address offset, type, and reset value of this register.
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