Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Programmers model
5.9.4 GICP_FRn, Filter Registers
These registers configure the filtering of event counter n. The GIC-600AE supports five counters, n
= 0-4.
Configurations
This register is available in all configurations.
Attributes
Width 32-bit
Functional group See 5.9 GICP register summary on page 163 for the address offset, type,
and reset value of this register.
Usage constraints
There are no usage constraints.
Bit descriptions
Figure 5-49: GICP_FRn bit assignments
Filter
31 30 29 28 16 15
0
Reserved
FilterEncoding
FilterType
Table 5-62: GICP_FRn bit descriptions
Bits Name Description
[31:30] FilterType Filter type:
0b00 Filter on core
0b01 Filter on INTID
0b10 Filter on chip or ITS
0b11 Reserved, no effect
[29] FilterEncoding
0 Filter on range
1 Filter on an exact match
[28:16] - Reserved
[15:0] Filter If the corresponding GICP_EVTYPERn.EVENT indicates an event that cannot be filtered, then the value in this
register is ignored.
When FilterEncoding == 1, counter n counts events that are only associated with an exact match of the
FilterType.
When FilterEncoding == 0, this field is encoded so that the first LSB that is zero, indicates the uppermost of a
contiguous span of least significant FilterType content bits, that the GIC ignores for the purposes of matching. For
example, setting Filter to:
•
0b11110111_11110111 matches with values of 0b11110111_1111xxxx for FilterType content
•
0b11110111_11110110 matches with values of 0b11110111_1111011x for FilterType content
•
0b11110101_11111111 matches with values of 0b111101xx_xxxxxxxx for FilterType content
Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved.
Non-Confidential
Page 169 of 268
To Next Page
Loading...
Need help?
General
