Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Programmers model
Bit descriptions
Figure 5-59: GICP_IRQCR bit assignments
31 10 9
0
SPIIDReserved
Table 5-72: GICP_IRQCR bit descriptions
Bits Name Description
[31:10] - Reserved, RAZ
[9:0] SPIID Sets the SPI ID that the GIC generates when a PMU overflow interrupt occurs.
If the value is less than 32, out of range, or not owned on chip for multichip configurations, the register
updates to 0 and no internal delivery occurs.
Set to 0, when the interrupt routes externally to a core that does not receive interrupts directly from
the GIC such as a central system control processor.
Creates a level-triggered interrupt if it is owned on chip. Otherwise it behaves as a normal message-
based SPI.
In a multichip configuration, the SPIID field must only be programmed to an SPI ID that the chip owns.
The relevant GICD_CHIPRn register controls the SPI ownership.
We recommend that if these registers are used, then the SPI must not be used for another device
either with a wire or as a message-based interrupt.
5.9.15 GICP_PIDR2, Peripheral ID2 Register
This register returns byte[2] of the peripheral ID. The GICP_PIDR2 register is part of the set of
performance monitoring peripheral identification registers.
Configurations
This register is available in all configurations.
Attributes
Width 32-bit
Functional group See 5.9 GICP register summary on page 163 for the address offset, type,
and reset value of this register.
Usage constraints
There are no usage constraints.
Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved.
Non-Confidential
Page 178 of 268
To Next Page
Loading...