ARM CoreLink GIC-600AE

Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Programmers model
5.8.1 GICT_ERR<n>FR, Error Record Feature Register
This register returns information about the Armv8.2 RAS features that the GIC-600AE implements.
Configurations
This register is available in all configurations.
Attributes
Width 32-bit
Functional group See 5.8 GICT register summary on page 147 for the address offset, type,
and reset value of this register.
Usage constraints
If GICD_SAC.GICTNS == 0, then only Secure software can access the contents of this register.
Bit descriptions
Figure 5-36: GICT_ERR<n>FR bit assignments
ED
31 16 15 14 12 11 10 9 8 7 6 5 4 3 2 1
0
DEUIFIUECFICECRPReserved
Table 5-46: GICT_ERR<n>FR bit descriptions
Bits Name Description
[31:16] - Reserved, RAZ
[15] RP Repeat corrected error count:
0 The GIC-600AE does not implement a repeat corrected error counter
[14:12] CEC Corrected error count:
0b000 The GIC-600AE does not implement a standard corrected error counter in GICT_ERR<n>MISC0
[11:10] CFI Corrected errors fault interrupt. Depending on the configuration, returns either:
0b00 The GIC-600AE does not provide a fault handling interrupt for corrected errors
0b10 The GIC-600AE provides a controllable fault handling interrupt for corrected errors
[9:8] UE Uncorrected error. Depending on the configuration, returns either:
0b00 The GIC-600AE does not provide an in-band uncorrected error reporting
0b10 The GIC-600AE provides a controllable in-band uncorrected error reporting
[7:6] FI Fault handling interrupt for uncorrected errors. Depending on the configuration, returns either:
0b00 The GIC-600AE does not provide a fault handling interrupt
0b10 The GIC-600AE provides a controllable fault handling interrupt
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