Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Components and configuration
Each wake_request signal is protected with odd parity. The parity signals are
wake_request_chk[<cpus>−1:0].
The level of the asserted wake_request[<cpus>−1:0] signal drops only when the Distributor leaves
reset, or when the core is woken and the GICR_WAKER.ProcessorSleep bit is cleared to indicate
that it is able to communicate with the GIC. The GIC supports a Wake Request block reset only
when the Distributor is also reset.
3.6.1 Wake Request AXI4-Stream interface
The AXI4-Stream interface enables the Wake Request block to communicate with the Distributor.
The AXI4-Stream interface does not exert back-pressure.
3.6.2 Wake Request configuration
The configuration of the Wake Request block is based on the number of cores in the system. There
are no other options to configure.
3.7 Interconnect
The GIC-600AE uses AXI4-Stream interfaces for communication between some blocks.
These blocks are:
•
Distributor to, and from, ITS
•
Distributor to, and from, Redistributors
•
Distributor to Distributor for cross-chip communications
•
Distributor to, and from, the SPI Collator
•
Distributor to, and from, the Wake Request block
All these interfaces use fully credited schemes where all messages are guaranteed to be accepted
without dependency on any other port.
Apart from the cross-chip communications, GIC-600AE provides an AXI4-Stream interconnect for
transporting messages. However, messages can be sent over an existing interconnect provided the
interconnect is free-flowing.
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