ARM CoreLink GIC-600AE

Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Components and configuration
CapabilityAttribute
Read Write Combined
8-bit reads to the Property table 4 0 4
Each transaction uses a unique transaction ID, and properties come from either the
GICR_PROPBASER or GICR_PENDBASER registers according to the destination. There is one copy
of the attribute fields for all GICR_PROPBASER registers and another for all GICR_PENDBASER
registers, so software must program these registers to a consistent value in all Redistributors.
The ACE-Lite manager interface cannot issue barriers or Cache Maintenance Operations (CMOs).
However, it can issue shareable, ReadOnce and WriteUnique, transactions if programmed to do so.
See 4.11 Memory access and attributes on page 64 for more information.
The a<x>user_m signal outputs the GICR_TYPER.ProcessorNumber of the core that is associated
with each transaction, but it can be ignored and it is not necessary to route it anywhere else.
If the Distributor and ITS both share the same ACE-Lite manager interface, the issuing capabilities
are cumulative.
3.1.4 Distributor Q-Channels
There is a single Q-Channel for clock gating the GIC-600AE Distributor. The Q-Channel interface
denies access when the Distributor is busy processing interrupts.
The Distributor also has a separate Q-Channel that enables power control for each configured ITS.
The GIC only accepts a low-power request when GITS_CTLR.Quiescent is set. If the Quiescent bit
is set, the Q-Channel qacceptn_its_<n> signal is asserted, and the GIC guarantees that the bus to
the relevant ITS is idle in both directions and that the ITS can be powered down. To perform wake-
on-LPI functionality, you can use GITS_FCTLR.PWE to disable the bus while the ITS is still active
and able to translate interrupts. If the bus is disabled, then when the qactive_gicd signal asserts
on the corresponding ITS, the system must re-enable the bus and program the GICD so that it is
ready to receive LPIs. The system must route the qactive_gicd signal to a power controller that
implements the following sequence:
1.
Power up the GICD
2.
Restore the GICD program state
3.
Turn on the associated ITS Q-Channel on the GICD, which allows the ITS to proceed
The qreqn* signals are synchronized internally, and can be driven asynchronously. See A.2 Power
control signals on page 251.
As the qactive output signal includes combinatorial and asynchronous inputs, then you must
consider qactive as an asynchronous output.
For more information, see the AMBA
®
Low Power Interface Specification.
Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved.
Non-Confidential
Page 29 of 268