Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Programmers model
EventID Event Description Filter
0x71 SPI_CC_LAT_WAIT SPIs waiting to be sent Chip
0x72 LPI_CC_LATENCY LPIs outstanding Chip
0x73 LPI_CC_LAT_WAIT LPI waiting to be sent Chip
0x74 SGI_CC_LATENCY SGIs outstanding Chip
0x75 SGI_LAT_WAIT SGIs waiting to be sent Chip
0x80 ACC Counter(n − 1) − counter(n − 2) every cycle. Prevents clock gating and Q-Channel
clock gating.
None
0x81 OFLOW Overflow of counter n − 1. Overflow counters cannot count overflows of the
counters that are using the OFLOW event.
None
5.9.3 GICP_SVRn, Shadow Value Registers
These registers contain the shadow value of event counter n. The GIC-600AE supports five
counters, n = 0-4.
Configurations
This register is available in all configurations.
Attributes
Width 32-bit
Functional group See 5.9 GICP register summary on page 163 for the address offset, type,
and reset value of this register.
Usage constraints
There are no usage constraints.
Bit descriptions
Figure 5-48: GICP_SVRn bit assignments
31
0
COUNT
Table 5-61: GICP_SVRn bit descriptions
Bits Name Description
[31:0] COUNT Captured counter value.
This field holds the captured counter values of the corresponding entry in GICP_EVCNTRn.
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