Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Programmers model
Bits Name Description
[9:0] SPIID Sets the SPI ID that the GIC generates when a fault handling interrupt occurs (<n>==0) or when an
error recovery interrupt occurs(<n>==1).
If the value is less than 32, out of range, or not owned on chip for multichip configurations, the register
updates to 0 and no internal delivery occurs.
Set to 0, when the interrupt routes externally to a core that does not receive interrupts directly from
the GIC such as a central system control processor.
In a multichip configuration, the SPIID field must only be programmed to an SPI ID that the chip owns.
The relevant GICD_CHIPRn register controls the SPI ownership.
We recommend that if these registers are used, then the SPI must not be used for another device
either with a wire or as a message-based interrupt.
5.8.9 GICT_DEVID, Device Configuration register
This register returns information about the configuration of the GIC-600AE GICT such as whether
an LPI or ITS is available.
GICT_DEVID was previously known as GICT_ERRIDR.
Configurations
This register is available in all configurations.
Attributes
Width 32-bit
Functional group See 5.8 GICT register summary on page 147 for the address offset, type,
and reset value of this register.
Usage constraints
If GICD_SAC.GICTNS == 0, then only Secure software can read this register.
Bit descriptions
Figure 5-44: GICT_DEVID bit assignments
31 16 15
0
NUMReserved
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