ARM CoreLink GIC-600AE

Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Functional Safety
◦ Chip2Chip
The following figure shows the distribution of interface protection within the GIC-600AE.
Figure 6-10: Interface protection distribution
ITS
PCIe
ACE-Lite
ITS
PCIe
SPI Collator
SPI interrupts
Distributor
FMU
APB
fmu_fault_int
(FHI)
fmu_err_int
(ERI)
Chip2Chip
Redistributor
Redistributor
CPU interface
CPU interface
PPI interrupts
Legend:
AXI4-Stream interconnect
protection (partial duplication)
Interrupt protection (parity)
Interface protection (AMBA FuSa)
RAM
(SECDED)
Logic
(duplication)
ACE-Lite
PPI interrupts
Point-to-point protection
Point-to-point protection is sufficient for wires and buffers that cannot cause multiple-bit faults.
An example of an interconnect component that might cause multiple-bit faults is a switch. A single
fault on a switch mux input can switch the wrong data, causing multiple bits to fail.
6.8.1 ACE-Lite interface parity protection
The GIC-600AE supports ACE-Lite interface parity protection for point-to-point connections from
the GIC-600AE to another functionally safe IP or FuSa interconnect. If a parity fault is detected,
the GIC-600AE flags a fault.
If this protection is not needed, software can disable the appropriate ACE-Lite Safety Mechanisms
by programming the FMU_SMEN register. Disable this protection when using an interconnect that
does not generate AMBA
®
parity.
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